1. Field of the Invention
This invention relates to a self-refresh control circuit for a semiconductor memory device, particularly a Dynamic Random Access Memory device (DRAM).
2. Description of the Prior Art
Recent advances in semiconductor dynamic memory device technology provide a self-refresh circuit on a single semiconductor chip having memory cells which can perform a self-refresh operation automatically and eliminate the timing or address control circuit formerly required outside the chip.
In general, this type of self-refresh circuit comprises an oscillator and a refresh address counter, which is provided for designating the address of memory cells during the refresh operation when the memory cells are on standby operation or not in the read or write mode.
In these circuits, the oscillator circuit which determines the frequency of the refresh operation is constructed using MOS-FETs. Generally, the operation of MOS-FETs becomes slower as the temperature of the device increases. Therefore, the frequency of the oscillator decreases in high temperature.
On the other hand, the current leakage of a memory cell increases roughly by a factor of two when the temperature rises by ten degrees. Accordingly, the frequency of the oscillator should be high enough so as to operate satisfactorily even in a high temperature environment. This results in the frequency of the refresh operation at low temperatures being higher than needed.
Further, because integrated circuits are manufactured through use of various processes, the characteristics of the circuits may vary. Therefore, it is necessary to set up the frequency of the oscillator with enough margin to compensate for those variations.
Accordingly, in general, the frequency of the oscillator is generally set to be 100 times the frequency needed in ordinary temperature conditions.
A refresh operation consumes a certain amount of power. For example, 256K DRAM consumes several milliamperes of current on standby operation. Because of this high power consumption, it is very difficult to operate a DRAM using a dry battry as a power source.
In order to eliminate these disadvantages, Japanese Laid Open Patent No. 59-56291 provides a memory device which automatically controls the frequency of the refresh operation so as to reduce the power consumption. This refresh control circuit comprises two leak current monitor capacitors, each of which is precharged to some respective predetermined level, and a voltage comparator circuit for detecting the voltage difference between the two capacitors and causing a refresh operation.
However, this refresh control circuit has following disadvantages. First, it is very difficult to design the characteristics of two capacitors, such as current leakage time or initial charge voltage, to simulate the current leakage of memory cells because the leak current monitoring system does not detect the current leakage time of the capacitor itself, but instead detects the difference between the voltages on the two capacitors. Therefore, unless the characteristics of the capacitor's are selected correctly, it is not possible to exactly monitor the current leakage time of the memory cells. Second, because the comparator circuit has a current flowing through it, it consumes power. This reduces the primary advantages of the circuit.